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TSMC Interview Experience Sharing: Resume Screen → GSAT Aptitude → Three Technical Rounds → Cross-fab Manager Panel

2026-06-01

TSMC is not a typical internet company. The cadence, question style, and leveling all map closer to semiconductor manufacturing and fab engineering. Even for software / firmware / IT engineering roles, process awareness, manufacturing discipline, and cross-fab communication carry weight equal to algorithms. This guide breaks the TSMC loop into five stages with templates and per-round samples.

Five-stage overview

W0  Resume screen: HR reviews degree level / department / internships / GPA
W1  GSAT aptitude test: 60 min math + verbal + figure reasoning
W2  Tech round 1: data structures + programming basics (C / C++ / Python)
W3  Tech round 2: semiconductor process + equipment + scenario questions
W4  Tech round 3: Verilog / C hands-on + system question
W5  Cross-fab manager panel: director / VP plus HR decide offer and fab placement

End-to-end is roughly 5-8 weeks. TSMC moves slower than IC design houses but more steadily. Fab placement (Hsinchu / Taichung / Tainan / Arizona) is usually finalized only at the manager panel.

Stage 1 — Resume screen

What HR reviews:

  1. Education: top-tier EE / CS / Mechanical / Physics / Materials departments are preferred
  2. Internships: semiconductor / IC design / firmware / test experience is a clear plus
  3. GPA: undergrad ≥3.5 / 4.3 is a safe bar; for masters, oral defense + research topic carry weight
  4. Project portfolio: GitHub repos / publications / patents help

A commonly overlooked detail: TSMC's resume system extracts keywords automatically. Spell out terms such as Verilog / SystemVerilog / Python / C++ / Linux / Foundry / TCAD / SPICE.

Stage 2 — GSAT aptitude test (60 min)

GSAT is TSMC's in-house aptitude system. Three modules:

Module Questions Time Topics
Math 25 25 min High-school to first-year college: probability, sequences, solid geometry
Verbal 15 15 min English/Chinese reading comprehension + vocabulary
Figure 20 20 min Rotation / folding / 3D unfolding

Important: GSAT scores by module; a single weak module tanks the whole test. The verbal section is typically the local-Taiwan candidate's weakest, so practice GMAT reading for timing.

Stage 3 — Tech round 1: data structures + programming basics

Mostly whiteboard or pen-and-paper. CoderPad shows up occasionally. Common buckets:

Frequent question 1: reverse a linked list (whiteboard)

typedef struct Node {
    int val;
    struct Node *next;
} Node;

Node *reverse(Node *head) {
    Node *prev = NULL, *cur = head, *nxt;
    while (cur) {
        nxt = cur->next;
        cur->next = prev;
        prev = cur;
        cur = nxt;
    }
    return prev;
}

Pitfall: candidates skip storing nxt and lose the chain when they update the pointer.

Frequent question 2: BFS level order with per-level maximum

from collections import deque

def level_max(root):
    if not root:
        return []
    q = deque([root])
    out = []
    while q:
        cur_max = float("-inf")
        for _ in range(len(q)):
            node = q.popleft()
            cur_max = max(cur_max, node.val)
            if node.left: q.append(node.left)
            if node.right: q.append(node.right)
        out.append(cur_max)
    return out

Frequent question 3: C pointer / memory question

"What does this print? Why?"

int *p = malloc(5 * sizeof(int));
for (int i = 0; i < 5; i++) p[i] = i * 2;
printf("%d\n", *(p + 3));
free(p);

The answer 6 is not the point. The follow-up "why not just p[3]? what is the difference?" probes the pointer + offset = array indexing equivalence.

Stage 4 — Tech round 2: process + equipment + scenarios

This round leaves pure algorithms behind and shifts into the semiconductor engineer mindset. Common topics:

Process basics

Equipment / metrology

Scenarios

Approach: answer with the engineer mindset of "collect data → categorize → conclude". Do not jump to a fix. Describe what questions you would ask, which logs you would inspect, and which metrics you would pull.

Stage 5 — Tech round 3: Verilog / C hands-on + system question

This round is led by the future direct manager. It is a deep technical dive. Common patterns:

Verilog frequent: 4-bit synchronous counter

module sync_counter (
    input  wire clk,
    input  wire rst_n,
    input  wire en,
    output reg  [3:0] q
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)      q <= 4'b0000;
        else if (en)     q <= q + 4'b0001;
    end
endmodule

Follow-ups:

  1. "Add an overflow flag" → add output reg ovf, set when q == 4'b1111 && en
  2. "Synchronous vs asynchronous reset?" → sync waits for clock edge; async takes effect immediately

C system question

"Implement memcpy and explain why strcpy cannot be replaced by memcpy."

void *my_memcpy(void *dst, const void *src, size_t n) {
    char *d = (char *)dst;
    const char *s = (const char *)src;
    while (n--) *d++ = *s++;
    return dst;
}

Key: strcpy stops on \0; memcpy ignores content and copies exactly n bytes.

Stage 6 — Cross-fab manager panel

30-60 minutes, led by a director or VP plus HR. Topics:

  1. Career planning: "Where do you see yourself in five years as an engineer?"
  2. Resilience: "TSMC has frequent overtime and on-call rotations — can you handle it?"
  3. Fab preference: "Which fab — Hsinchu, Tainan, or Arizona — is your top choice?"
  4. Compensation: base + bonus + RSU. TSMC RSU usually vests 50%/50% across two years.

Comp negotiation: refer to TSMC's published P5-P9 ranges on levels.fyi. Provide a range, not a single number. Stress base + bonus + RSU together.

Three fab differences

Dimension Hsinchu Fab12 Tainan Fab18 Arizona Fab21
Lead nodes 5nm / 3nm 3nm / 2nm 4nm / 3nm
Housing cost High Medium Medium (Phoenix)
OT intensity High Medium-high Medium
Comp multiplier 1.0x 1.0x 1.5-1.8x (USD)
Remote / WFH Rare Rare Some hybrid

Six-week prep plan

Week 1-2  GSAT: 30 min math + 15 min verbal daily; finish 2 full mock tests
Week 3    DS + C: 30 whiteboard problems covering list / tree / graph basics
Week 4    Verilog: 4-bit counter / FIFO / FSM, 5 each, with testbenches
Week 5    Process + equipment: TSMC technical white papers + Wikipedia lithography / CMP / etch
Week 6    Manager panel + resume: 3 career stories + fab preference rationale + comp range tuning

FAQ

Q1: Do TSMC software engineers need Verilog? A: Depends on the role line. Design / DV / Physical Design require it. Pure IT / DevOps can skip it but RTL fluency is a plus.

Q2: Is a poor GSAT score recoverable? A: HR evaluates holistically — strong resume + strong technical rounds can still get you to the manager panel, but aim for at least 60% per module.

Q3: Does the manager panel reject candidates? A: Yes. Tech rounds pass at 60-70%, the manager panel at about 70%, so overall offer rate sits at 30-40%.

Q4: Hsinchu vs Arizona pay gap? A: At P5, Hsinchu monthly is roughly NT$80-100K (14-16 months a year). Arizona converts to roughly USD $110-140K base, a 1.5-1.8x lift offset by cost of living and being far from family.

Q5: Does TSMC hire foreign nationals? A: Yes. Hsinchu / Tainan support work visas. Arizona hires directly via H-1B / L-1 and offers an annual internal transfer track.

Closing

TSMC is neither a pure RTL house nor an internet algorithm shop. It expects engineering rigor, semiconductor literacy, and cross-fab communication simultaneously. If you are prepping for a TSMC interview, ping WeChat Coding0201 — share your fab preference (Hsinchu / Tainan / Arizona) and role line (Design / DV / IT / Software) and we can map the prep direction and frequent questions for you.

Need real interview questions? Reach out on WeChat Coding0201, get the question bank.

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